Memory devices such as dynamic random access memory (DRAM) devices can include delay elements to assist with regulating timing of certain signals and functions. Present techniques for implementing delay elements can include a resistor-capacitor (RC) network disposed between two inverters. Such networks are easy to implement and can be efficient with respect to chip space compared to alternative implementations. However, the actual delay of such delay elements can vary significantly, such as about 30%-35% with respect to process, voltage and temperature variations (PVT).